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ADV7842 Occasional SD output failure

Question asked by adhawkins on Jun 20, 2013
Latest reply on Jun 24, 2013 by GuenterL



Occasionally when switching between inputs on the ADV7842, it appears that our downstream TI processor fails to correctly lock on to the video.


When we've seen this happen, we've had no input connected to the appropriate SD input (CVBS, SVideo or RGB sync on Composite), and the 7842 is therefore set to free run. However, our TI processor appears to fail to lock on to the video.


We've used a 'scope to check the signals coming out of the ADV, and as far as we can tell the clocks, syncs and even SAV and EAV data is identical in the two cases.


Attached are two register dumps from the 7842 showing the working and non-working case. Also attached is a list of the differences between these two register sets, which amounts to a total of 16 registers (in the differences file, for each change the first value listed is the non-working case, the second the working case). The vast majority of these are undocumented, and if I try to change them then my changes are lost, so I suspect they are readbacks of some sort. Can you tell us what the function of these different registers is? Is there anything in there that could indicate a cause of the issue?


Of particular interest is that register 5a in the SDP map always seems to contain a higher value when no video is being detected. Only bit 0 of this register is documented (SDP_VIDEO_DETECTED), what do the other bits mean? Could they indicate some sort of issue with the free running of the SDP block?


By experimentation, we have found that resetting the SDP block before re-configuring it when changing inputs seems to work reliably (although it's difficult to be 100% sure due to the intermittent nature of the problem). Is resetting this a valid thing to do? Should we also be resetting the SDP memory?


Should we also be applying this approach to the CP and HDMI blocks? Can these be reset individually?


We are providing EDID for the HDMI ports from the 7842's RAM. Presumably if we reset the 7842 as a whole, there will be a momentary loss of EDID data to any sources that are connected?


Any advice you can offer would be appreciated.