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The external interrupt for ADSP2136X/46X

Question asked by Tao.Cheng on Apr 21, 2010
Latest reply on Apr 21, 2010 by DivyaS

Hi,Guys,

      In <ADSP_2136x_PGR_rev1-1.pdf> P4-36, "The processor detects a level-sensitive interrupt if the signal input is low
(active) when sampled on the rising edge of PCLK/2. A level-sensitive
interrupt must go high (inactive) before the processor returns from the
interrupt service routine. If a level-sensitive interrupt is still active when
the processor samples it after returning from its service routine, the processor
treats the signal as a new request. The processor repeats the same
interrupt routine without returning to the main program, assuming no
higher priority interrupts are active.
The processor detects an edge-sensitive interrupt if the input signal is high
(inactive) on one cycle and low (active) on the next cycle when sampled
on the rising edge of PCLK/2. An edge-sensitive interrupt signal can stay
active indefinitely without triggering additional interrupts. To request
another interrupt, the signal must go high, then low again."

 

Does that means that ADSP2136X/46X external interrupt could only support low level, or falling edge, and not support high level, or raising edge?

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