My initial response would be that the output pins go active during the reset but let me check with the 7180 expert
The pins go into and undetermined state during reset. Here's a previous past which talks about this issue.
Is the undetermined state damaging? Would this undetermined state be capable of driving current?In this application, there is a pin muxing scheme that has the processor pin set to an output (default as a UART TX) muxed on the same pin as is used as the digital video input. So, if the ADV7180 is capable of sourcing or sinking current in the undetermined state, I would suppose this UART TX output could be a problem (effectively two outputs battling each other)? Could this be damaging?
Potentially yes, however to date we haven't seen a damaging problem. It is always a good Idea to put a 33 Ohm series resistor on the outputs if it's going into a mux'd bus to limit potential current and limit EMI/ringing issues. As is normal the amount of time buses are kept in contentions should be kept to a minimum.
Is there a limit on output current draw? I didn’t see anything in the datasheet.
The output voltage limits have currents specified that give you an idea but the output max current drive is not characterized.
So, in this thread we discuss obvious issues with bus contentions and needing series resistance to limit current when two devices are both set at outputs and actively driving the line. How would I go about identifying the proper resistance needed? What is the maximum current that will not cause damage or latch-up?
The primary purpose of the output series resistor is to control ringing on the bus caused by signal edges. A secondary benefit is that is reduces current when bus contention occurs.
Now lets make an assumption we have 2 devices, both with 22 Ohm series resistors on their output. One device is driving high to 3.3V and the other device is pulling low. And assume the device output impedance is 25 Ohms (not uncommon and can be determined from the IBIS model). Then the maximum current is 3.3 / (25 + 22 + 22 + 25) = 35mA 35mA will not cause a latch up only thermal issues.
You can see if you have a contention issue by monitoring the bus voltage with a scope and if it goes to ~1.5V then bus contention is occurring.
The only real problem I see is you purposely kept the bus in contention for a long time. If one chip is driving 20 pins high then that chip may have thermal issues just driving 20 pins with 35mA each. Extended times like 1-2 minutes seconds may cause thermal damage, short periods < 100ms will not be a problem. It's a thermal time constant/cooling issue. Again I have no characterization on this, just past experience.
The maximum current to cause latch up has not been characterized.
On a slightly different note, latch up is caused by current being injected (usually from an ESD hit) into a pin causing the ESD protection circuit to latch up, SCR like. Its been a very long time since I've ever seen a latch up issues. ESD protection circuits have gotten much better. Bus contention will not cause latch up. Bus contention over long periods of time cause thermal issues with the parts and in many cases the parts can handle the thermals just fine.
I'd like to connect the outputs to a memory bus. How can I Tristate them or is this not possible?
Check out TRI_LLC and TOD registers, theyll tri-state the output pins
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