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Zed HDL Reference Design for ADV7511 HDMI transmitter: No Top-level Input clock for the design.

Question asked by adamo79 on Jun 18, 2013
Latest reply on Jun 20, 2013 by adamo79

Hi all,

I'am trying to rebuild the reference design Zed HDL Reference Design for ADV7511 HDMI transmitter and I got the following warnings:

EDK:1954 - No Top-level Input clock for the design.

EDK:3712 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Frequency of the interconnect's clock port could not be determined.

EDK:3712 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Frequency of the interconnect's clock port could not be determined.

EDK:3712 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0 - Frequency of the interconnect's clock port could not be determined.

 

How can I solve this problem?

I'm using version 14.5 of Platform Studio

 

Thanks in advance.

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