I'd like to use the REFCLK multiplier, but I want to know if there are any tradeoffs.
The benefit of using the PLL multiplier is that it allows you to use a low frequency clock source (a crystal oscillator, for example).
You sould avoid using the PLL multiplier, however, if your application has a very demanding phase noise requirement. The PLL multiplier performs well, but the performance of its integrated VCO cannot compete with a high quality RF frequency source. Furthermore, the PLL amplifies the phase noise at its input (within the loop bandwidth of the PLL), so applications that need very good close-in phase noise performance are not well suited for using the PLL multiplier.
It's worth noting that the performance of the multiplier is product specific. Older devices (AD9851, for example) exhibit higher phase noise than newer products (AD9910, AD9911, AD9912 and AD9913 all have stronger performing PLLs)
Based on this and LoujieC's recent FAQ, does this mean it is potentially better to drive my DDS (AD9910) with an external PLL synth clock than using the internal PLL ? For example, I am currently using an external 10 MHz xtal oscillator with the internal PLL to generate a 1 GHz sysclock. If I generate the 1 GHz externally using a better PLL and then drive the DDS directly, can we expect better performance from the output of the DDS in terms of phase noise and spurious levels etc ?
I think there is no general rule saying that an external PLL is always better than the internal. But since an external PLL can have the advantage of being isolated from the IC package and have a dedicated resource on its own. Then potentially it can have better performance than the internal PLLs. From what I've known, the motivation of having an external PLL is due to the limited performance of the integrated VCO in terms of phase noise. Thus achieving the specs that have demanding phase noise requirements makes the solution of external VCO attractive.
Retrieving data ...