My own signal processing system consist of two pieces of board.
In each board, there are one TigerSHARC processor is booted, which then boots the other processors.
After booting sequence, the system operating well.
During booting sequence, I tried to check the timing of nBMS signal using scope.
But the result was that we not expected. The timing of the "nBMS" signal was different in each board.
Is it possible that the nBMS signal's timing changed by any setting of register values?
I want to know the timing of nBMS signal operating as CS for EPROM boot.
Let me show the right timing diagram of nBMS signal.
Please reply at the earliest!