I cannot find the minimum specification for the Master Reset pulse width in the data sheet. Is there one?
The Master Reset is an asynchronous operation. It should be issued after power-up. A Master Reset places the internal registers in their default state. The last columun of the register map in the data sheet shows the default state values of each register. The minimum Master Reset pulse width is typically not characterized. The rule of thumb is a minimum of 5 to 10 system clock periods is more
than sufficient for the minimum master reset pulse width.
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