I didn't reach to run the AD80066 since the beginning of this month....
I have three questions about the AD80066 :
- There are minimum values for the period of the ADCCLK clock, but is there a maximum value?
- If the sampling clock of the ADC is internal (8Mhz or 24Mhz selected by the configuration bit D1) or external (the frequency of ADCCLK)
- When I read the timing diagrams of the 1-Channel Mode, Shannon theorem seems to be not respected because the frequency of the ADCCLK and the frequency of the analog input are the same.
For the moment, i try to use the SHA 1-Channel Mode. I respect perfectly the timing diagram of this mode, but the data is always the same (all bits in high level).
I use a frequency of 1Mhz for CDSCLK2, ADCCLK and the analog input, is it too slow?
What are the possible origins of this problem, is there any additonnal constraints which are not mentionned in this timing.