So,my design is working with my serial clock out. But ... I have another problem, I see a synchro between clock domain problem.
The part of the design that is involved, is one input that come from USB=>I2S converter. USB/I2S converter output master I2S (BCLK,LRCLK), that is derived from it's quartz I think (12 MHz for USB). Sampling rate is at 44.1kHz
ADAU1446 is clocked from 11.2896 Mhz (own quartz not related to 12 MHz)
On other part, I output I2S to AES/EBU transmitter (to AES/EBU receiver and next DAC). I output master clock to AES/EBU transmitter.
With sine tone generator inside ADAU1446 no problem. But when I output data that come from USB/I2S I have some "clic" along the time. Problem of clock domain, it seem obvious. Dejitter window can'to do anything because clock will derivated.
So I will to synchronize ADAU1446 on USB/I2S clock (and transmitter). So I configure input to be slave to clock domain of USB/I2S (0), output to be slave of the same clock domain(11) (I send this clock domain one LRCK0/BCLK0 and LRCLK11/BCLK11).
And I set "start cycle pulse" on clock domain 0.
It works, I've got sound, less clic,just one small remaining between 3 to 10 by second.
It's always a problem of clock domain, because if I try to "tune" 11.2896 quartz, clic change rate, and there is even a good tune, where there is no clic anymore. But this solution of tuning is not acceptable.
Dejitter window doesn't change anything on problem (0 to 63 do nothing) because clock derivate
So questions :
Is it possible to clock ADAU1446 totally slave ? (with my séparate clock). What register config should I made ?
Should I have synchronous clock ? If I run ADAU1446 at 12MHz (what is accetable) from USB clock, clock will be synchronous ? Does it solve problem (I will try)
What are other possibilities ? Should I do PLL between to clock (12=>11.2896) ? And even if I do that I will be not "that synchronous" between clock domain, but I will not derivate anymore, so dejitter can perharps do job for me ...
ADAU1445 would solve problem with resampler, but I will avoid this !
Datasheet seem to claim that ADAU1446 can be whole slave of one master clock ... I don't see where is the fact I missing.
In last, a typo error in datasheet p42, clock domain master.slave select. In slave config,
0=>Clock domain 9
1=>Clock domain 10
2=>Clock domain 11
3=>Clock domain 3
4=>Clock domain 4
this error is confirmed by SIgmaStudio that do good config but datasheet is not good.
Thanks for answer !