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SHARC Hardware Acceleration: Simple Question

Question asked by Troy on Apr 6, 2010
Latest reply on Apr 20, 2010 by hemanth



My name is Troy and I'm currently in my final year of Electrical Engineering.


I'm doing a report and presentation for my DSP course (we're using the TS-201) on SHARC FIR/IIR/FFT hardware accelerators (especially when compared against the performance of the TigerSHARC).


My question is: is it theoretically possible to use more than one of the FIR/IIR/FFT accelerators at once?  Based on the functional block diagram of the SHARC, it would appear that there could be problems if the accelerators need to compete for memory access resources, but otherwise, is there anything limiting their simultaneous use?


Additionally, if anybody has any resources they've found other than Hardware_Accelerators_SHARC.pdf and the hardware reference manual that highlight SHARC hardware acceleration or compare it against some other processor's capabilities, I would be much appreciative.