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BF561: Edge Sensitive Interrupt and read from FIOx_FLAG_D register

Question asked by Comm on Mar 19, 2010
Latest reply on Mar 19, 2010 by Comm

Hallo,

 

I have an edge sensitive interrupt configured.

 

In the ISR the coresponding bit in the FIOx_FLAG_C register is set to clear the latched interrupt flag.

 

After this step the coresponding bit in FIOx_FLAG_D will be cleard. So it is not possible to read the right level from the pin.

 

With best Regards

Franz

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