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ADAU1761 I2S signal configuration

Question asked by jaguarondi on Mar 12, 2010
Latest reply on Mar 12, 2010 by JeradL

Hi,

 

I'm having difficulties to get the 1761 issuing a correct I2S data output. What I get now is the data from the ADC on 15 bits instead of 16 like configured. Without signal, inputs internally polarized at VDD/2, I get the following values from the I2S data out: 0 -> 0x0000, 1->0x0001, -1->0x7FFF. If is connect the input to gnd, I get 0x3FFF and to VDD, I get 0x4000. If I shift everything 1 bit to the left, the codec works perfectly.

 

Now only the ADC has that problem, the DAC works correctly, minimum output voltage corresponds to 0x8000 I2S input data and maximum to 0x7FFF.

So what I currently do is read the I2S data, shift one bit left, send it back to the codec and I get the same signal at the output and input pins.

 

Here's what I checked already:

- values have been confirmed with a logic analyzer, so it's not a MCU configuration issue

- I bypass the DSP, I followed the app note to use the 1761 like a 1361 configuring all registers like described

- R16->LRDEL is set at 00 to get 1 bit clock delay on data, which is correct on the logic analyzer, the LSB affected by the noise can correctly be identified just right after the LRCLK signal change

- R16-> BPF is set to 1 which is undefined on the datasheet but from these forums, it seems to be the 32 bits per LRCLK setting

- As a test, I connected the output of mixer 1 (record path) to mixer 3 (playback mixer) and could verify that the signal I get on the output lines is correct and identical to the input signal, no shift or whatever on the signal so this means that the signal is correct at the ADC input

- Configuration: MCLK is 12.5MHz, R0=0x01 (no PLL, 256x oversampling), R15=0, R16=0x40 (stereo 16 bits I2S), R17=R18=0 (48KHz), R19=0x13 (both ADC on), R20=R21=0 (no attenuation), , R65=0x7F, R58=R59=0x01, R66=0x03 (all clocks enabled). Except the mixers configurations, everything else is default.

- Here I am, any idea what could be wrong?

 

By the way, AN-1007 says to set R65 to 0xEF which seems to be wrong and should probably be 0x7F as the bit 7 is reserved in that register. Anyway, both values do the same for me.

 

Thank you,

David

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