I sometimes get a question like how many SDRAMs can I connect to the processor?
Can I use SDRAM modules?
Or, why is there no fan-out ratio (maximum number of inputs driven by 1 output) in the datasheet?
Unlike some FPGAs or ASICs, processors do not specify a maximum number of inputs for each output.
The output loading of any pin can usually be determined by the total capacitive loading. Except for things like LEDs, most digital loads require very little DC current. Capacitance is the primary issue. There is usually an absolute maximum capacitance listed in the datasheet of perhaps 200pF. If each input had 5pF that would be 40 inputs if the connecting trace did not have about 2 or 3pF per inch.
More often, frequency of operation is limited by the rise and fall time curves shown for each output type in the datasheet.
A good example is SDRAM loading on the External Port or EBIU signals. The loads are often a combination of SDRAM inputs, flash inputs and trace capacitance. The rise and fall time reduction as capacitance increases limits the maximum operating frequency.
To operate near full bus speed of 100 or 133MHz, the capacitive limit works out to between 4 and 8 SDRAMs for most applications. Modules with 8 SDRAM chips are not likely to run at full speed.
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