I have some trouble with the EPPI0 interface on the BF548 core 0.2.
There is a delay between start peripheral and the actual moment the data is clocked out
which I can't explain.
I’m using the following construction:
Timer3 is used to generate a clock signal,
*pTIMER3_CONFIG = 0x0009;
*pTIMER3_PERIOD = 0x00D2;
*pTIMER3_WIDTH = 0x0020;
PPI0 is clocked externally by Timer 3,
PPI0 drives 8 bit data in DMA Auto buffer mode,
DMA is configured as:
*pDMA12_CONFIG = 0x1020;
*pDMA12_START_ADDR = &Data;
*pDMA12_X_COUNT = 0x0010;
*pDMA12_X_MODIFY = 1;
PPI is configured as:
*pEPPI0_CONTROL = 0x0000040E;
The SCLK is running at 100.8 MHz CCLK at 504 MHz
First DMA is enabled, next PPI, and after a ssync() finally timer3.
After timer3 is enabled to generate the clk pulses, the first data is clocked AFTER 6 pulses see attached
image, the first spike is no problem this is ignored by the other hardware which is also clocked by Timer3.
Other peripherals which are using DMA at the same time are: SPORT0 and SPORT1, which receive data, however
they run on a different DMA controller (DMAC1).
- Why are there 6 pulses? the HWREF man mentions on page 26-6 there may be up to 2 cycles needed.
- Is this delay "fixed" for e.g. different core revisions so a software workaround can be created?