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BF51x doc clarification

Question asked by ChipBrown on Mar 4, 2010
Latest reply on Mar 5, 2010 by JoeT

I'm looking at booting via UART for test/diag on a BF51x, and the comments about HWAIT confuse me.  I've never used this boot mode, and I think there may be some cut/paste stuff going on in the HW Ref, but I want to be sure I'm not missing something by assuming too much.

 

From the BF51x HW Ref doc 0.1:

 

During ADSP-BF51x boot operation, the host device more likely relies on
the RTS output of UART1. Then, the use of HWAIT becomes optional. At
boot time the Blackfin does not evaluate RTS signals driven by the host
and the UART1 CTS input is inactive. Since the RTS is in a high impedance
state when the Blackfin processor is in reset or while executing preboot, an
external pull-up resistor to VDDEXT is recommended.

 

This looks like a copy/paste from the BF54x HW Ref.  The UART1 references make no sense on the BF51x, since only UART0 can do UART boot mode (mode 0111), and the 51x does not support RTS/CTS on its UARTs.

 

I believe what it should say about CTS is essentially the same as the BF53x (HW Ref v3.1):

 

As indicated in Figure 19-33, the HWAIT feedback may connect to the
Clear-To-Send (CTS) input of an EIA-232E compatible host device,
resulting in a subset of a so-called hardware handshake protocol. At boot
time the Blackfin does not evaluate any Request-To-Send (RTS) signal
driven by the host.

 

So the HWAIT signal could drive the host's CTS and everything should work.  Is that a fair assumption?  That looks like how the EZ-Board is wired.

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