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ADF4108 Input Sensitivity,  AD9788 Clock Noise

Question asked by roadrunner Employee on Feb 23, 2010
Latest reply on Mar 1, 2010 by dawid.powazynski

A few questions on specs for the ADF4108, and AD9788

 

1. ADF4108 - Data sheet says input sensitivity is +/- 5 dBm while Figure 5 shows a sensitivity of -22 dBm at 6 GHz. Which one is right?

 

2. AD9788 - The data sheet doesn't tell us what noise spectral density to expect with the internal clock multiplier operating as an x2, x4 or x8. Doesn't say what the PLL loop bandwidth is or what the expected close-in phase noise (jitter) might be. This is an important parameter for us as it contributes to the output signal noise floor. We intend to run the DACCLK at 224 or 448 MHz with an Fout of 70 or 140 MHz.

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