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Writing to SPORT0_TX REGISTER

Question asked by Sid on Feb 19, 2010
Latest reply on Feb 22, 2010 by gvasanth

Hi All,

 

I am using a custom board consisting of BF533 Blackfin processor Silicon Revision 0.5.

 

I am trying to implement SPORT UART Interface using SPORT0 without DMA. For basics, I am just trying to send data over DT0PRI to ensure that TX Port is functional. I have initialised SPORT0 and I get valid clock on TSCLK. But when I try to write data to SPORT0_TX register, I see that it fails to get written to the TX register.

 

Is there anything that I am missing? Is there any anomaly that needs to be implemented?

 

I am attaching my source code here for reference.

 

EX_INTERRUPT_HANDLER(SPORT0_ISR);
EX_INTERRUPT_HANDLER(SPORT0_ERROR_ISR);

 

int main( int argc, char *argv[] )
{
    //defines
   
    int a;
    unsigned char uart_sel;
    volatile unsigned short sport0_status;
    volatile unsigned char sport0_rxdata;
    volatile unsigned char sport0_txdata;
   
    /* Begin adding your custom code here */
    Init_Interrupts();
    SPORT0_initialisation();

 

    return 0;
}

 

void Delay(ULONG n)
{
    ULONG i;
    for(i = 0;i < n;i++);   
}

 


void SPORT0_initialisation(void)
{
    *pPLL_DIV = 0x04;
   
    *pSPORT0_TCR1 = 0x0000;    
    *pSPORT0_TCR2 = 0x0000;    
      
    // TX config
    *pSPORT0_TCLKDIV = 0x1458;        //100000000/2*9600
    *pSPORT0_TFSDIV = 31;           
    *pSPORT0_TCR2 = 16;
    *pSPORT0_TCR1 = ITCLK | ITFS | LATFS| TFSR| LTFS;
    ssync();

 

   
    *pSPORT0_TCR1 |= TSPEN;        //tx enable
    ssync();
}

 

 

 

void Init_Interrupts(void)
{
  
    // configure interrupt  
    *pSIC_IAR0 = *pSIC_IAR0 & 0xffffffff | 0x00000000;    // map SPORT0 Error Interrupt -> IVG7
    *pSIC_IAR1 = *pSIC_IAR1 & 0xffffffff | 0x33322221;    //
                                  
    register_handler_ex(ik_ivg7, SPORT0_ERROR_ISR, EX_INT_ENABLE);
    register_handler_ex(ik_ivg9, SPORT0_ISR, EX_INT_ENABLE);     
  
      *pSIC_IMASK = SPORT0_ERR_IRQ | DMA2_IRQ;
    ssync(); 

 

}//end Init_Interrupts

 

 

 

EX_INTERRUPT_HANDLER(SPORT0_ISR)   
{
    int i;
    unsigned short statreg=0;
  
      *pDMA2_IRQ_STATUS = 0x1;
    ssync();

 

    while ((*pSPORT0_STAT & TXF)==1);
    *pSPORT0_TX = (unsigned short)0xCC0A;    
    ssync();
    while ((*pSPORT0_STAT & TXHRE)==0);
   
    while ((*pSPORT0_STAT & TXF)==1);
    *pSPORT0_TX = (unsigned short)0x8061;    
    while ((*pSPORT0_STAT & TXHRE)==0);
    ssync();

 

    while ((*pSPORT0_STAT & 0x0040) == 0)        // While HOLD not empty....
    {asm("nop;");};
   
    for(i=0;i<0x40000;i++)   
    {asm("nop;");};
   
    *pSPORT0_TCR1 &= ~0x0001;                    // Disable Transmit INT    

 

 

 

}

 

EX_INTERRUPT_HANDLER(SPORT0_ERROR_ISR)   
{
    unsigned short status;  
   
   
    status = *pSPORT0_STAT;  
  
    if (status & TUVF){ //W1C
        *pSPORT0_STAT = status | TUVF;
        ssync();
        txUnderflowStatus++;
        ssync();
    }
    if (status & TOVF){ //W1C
        *pSPORT1_STAT = status | TOVF;
        ssync();
        txOverflowStatus++;
        ssync();
    }
  
    if (status & TXHRE){ //
        txHoldRegEmpty++;      
        ssync();
    }
    if (status & TXF){ //
        txFifoFull++;
        ssync();  
    }

 

}

 

Thanks and Regards,

Sid

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