I am using ADSP21369 in my project and using the SPI slave boot mode. I want to know if I have to keep the chip select line LOW till the whole file is transferred or I can bring that back inbetween.
When booting, the ADSP-2126x/2136x/2137x/2146x processor expects to receive words into the RXSPI register seamlessly. This means that bits
are received continuously without breaks in the CS link. So it means you need to keep the CS low.
This information is available in the VisualDsp++ 5.0 loader and utilities manual, page 6-8. I think this is what you were looking for. Please let me know if you have further questions.
During the SPI slave booting, the CPHASE=1 (given in page 14-47 in ADSP-21368 HRM), and according to this mode, if you look at ADSP-21368 HRM page 6-28, it states,
When CPHASE = 1, SPIDS may either remain active (LOW) between successive transfers or be inactive (HIGH).
So according to this, the chip select can be 'high' between successive transfers.
Hope this helps,
Thats correct when CPHASE=1 the chip select signal can be manually controlled by the software. But is this true in while bootloading i.e. do we have to keep it low till the whole file is loaded?
I have tried by bringing it low for the whole file transfer and it works but it does not work when I bring the chip select line up and down inbetween transfers.
Thanks Deepa. Thats what I was looking for.
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