I'm using a Blackfin BF548 processor in a system which requires two synchronized SPORT's in receiving mode,
both RSCLK0 and RSCLK1 should have their rising and falling edge synced.
After some experimentation I found a solution by using a Timer ISR.
BF548 core 0.2
CCLK 528 MHz
SLCK 105.6 MHz
VisualDSP 5.0 Update 7 + HPUSB ICE
Code ANSI C
Timer3 generates a certain PWM pattern (Period 0xD8, With 0x20).
SPORT0 and SPORT1 RSCLK = 52.8 MHz
The Timer ISR is called when the timer period expires, on the first interrupt I activate SPORT0, the second interrupt activates SPORT1 and masks(disables) any further interrupts.
SPORT0 and SPOR1 are preconfigured for DMA autobuffering, and only need their RSPEN bit set to 1. The ISR is shown below. When I use a call to a function which enables the SPORT it works, the clocks are in sync, after the second interrupt.
However, if I try to set the RSPEN bit direct, *pSPORT0_RCR1 |= 0x0001; the processor hangs, and needs a reboot ? Why can't I enable the SPORT directly from an ISR?
*pTIMER_STATUS0 |= 0x00000008;
// *pSPORT0_RCR1 |= 0x0001; Doesn't work?
Startad = 1;
// *pSPORT1_RCR1 |= 0x0001; Doesn't work?
*pSIC_IMASK2 &= 0xFDFFFFFF;
} // end IVG 11
*pSPORT0_RCR1 |= 0x0001;
*pSPORT1_RCR1 |= 0x0001;