AnsweredAssumed Answered

Odd behavior with TIMER ISR, GPIO & PPI using BF561

Question asked by Efreak on Feb 9, 2010
Latest reply on Feb 23, 2010 by kaushal



I have an application in which I have configured 4 general purpose timers to drive an imaging sensor. I am reading the data from that

sensor via PPI0 and the timers and PPI0 produce interrupts. One of the timers that that drives the sensor also drives the PPI0 clock.

In the ISR for the that timer (PPI0 clock), I toggle flag pins with the intent to have the flag pin toggle in sync with the PPI0 clock. However,

when the entire system is enabled, the gpio pins fluctuate(jitter) when they toggle by as much as 1 PPI0 clock period.


However, if I set the enable bit of the PPI0 register to zero (disable the PPI0 peripheral), the jitter goes away and the flags toggle perfectly in sync with

the PPI0 clock (timer output).


Now I would expect to see some jitter, however I would expect to see it jitter by the system clock period not the PPI0 clock period.


I have tried arranging the interrupt priorities and that doesnt seem to help. Any ideas??


System info


cclk = 600MHz

sclk - 120MHz


TIMERS (all pwm outputs, with interrupts enabled

TIMER1 = 60Hz < ---resets software counters for both TIMER3 and TIMER5 on this interrupt

TIMER2 = 1.5MHz

TIMER3 = 3MHz <--pflags toggle on this interrupt

TIMER5 - 15kHz <--dma access from external memory to L1 on this interrupt


All timers are enabled at the same time and are on frequency and in sync with each other.