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ADI_NFC_ECC_MODE - documentation

Question asked by gpetrowitsch on Feb 5, 2010
Latest reply on Feb 8, 2010 by vapier

Dear all,


is there any documentation available that details the features and differences of the ECC modes used in the driver for NAND flash controller of the BF548?

I can find these modes in the source code, but I can't find out what they do in detail:


    ADI_NFC_ECC_MODE_NON_SEQUENTIAL = 0,    /* ECC stored non-sequentially in NFD Spare area        */
    ADI_NFC_ECC_MODE_SEQUENTIAL,            /* ECC stored sequentially in NFD Spare area            */
    ADI_NFC_ECC_MODE_NAND_BOOT,             /* ECC stored in the format compatible with NAND boot   */
    ADI_NFC_ECC_MODE_NAND_BOOT_NO_ECC,      /* Loader stream already contains the parity data       */
    ADI_NFC_ECC_MODE_DISABLE                /* Disable Error correction/Discard HW generated ECC    */

Is there some more detailed information on how ECC data is stored and why there are different modes etc.?


Thanks for any help!