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AD9910 PLL stability

Question asked by harrycheung on Jun 15, 2013
Latest reply on Jul 4, 2013 by harrycheung

Hi all,

 

I have been testing the AD9910 Eval Board. The ref_clk frequency is 26MHz and I set the PLL multiplier to (x38). When I program the DDS not to output anything, the sync_clk is stable, so I infer that the system clk is stable. However, when I program the DDS to output a 250MHz signal, the output waveform sustains for a minute then disappear. The sync_clk signal, which should be one-forth of system clk frequency, also vanish. Is there any reason that the PLL is not locked when the DDS is generating a non-zero signal? The output waveform is stable if I program the system_clk to be less than 400MHz.

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