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Analog Devices 14 Bit ADC (AD9640BCPZ-150) Distorted Sampled Output

Question asked by asimlink on Jan 13, 2010
Latest reply on Jan 27, 2010 by CraigG

Hi Friends,


I have designed a board which has AD9640BCPZ-150 analog to digital converter from Analog  Devices.

This ADC is interfaced to a  Spartan3AN FPGA. The ADC is seemingly producing distorted output (or call it missing code problem). The detail of  this trouble is as under:

 

Trouble Description: The captured  analog data produced by any channel of this AD9640 has distortion. This  distortion is produced by the steps that are suddenly introduced in the output  data at some particular voltage levels. The schematic of our  AD9640 interface can be found in attached  “Schematic.pdf”.

I have verified the integrity of  all data, clocks and control signals between ADC and FPGA and I do not find any  trouble in it.


I have performed a test. In this test I generated the differential Sawtooth Signal from on  board 14Bit , DAC2904 DAC and connected the output of this DAC to the input of  this AD9640 in following fashion:

ADC_D_A+ =  DAC_D+

ADC_D_A- =  DAC_D-


In following picture you can see the Output of the 14 bit DAC captured through Xilinx Chipscope pro in RED color. and the captured output of the AD9640 channel A in Blue color.


Busplot.jpg:

Busplot.JPG



Dataview.jpg:

dataview.JPG


 

 

I ran the test on  our other boards as well (same design containing AD9640BCPZ-150 ICs), but the result is  same. That is we see sudden steps in the sampled ADC output, regardless of the  ADC channel being monitored. We have this problem on 10 prototype boards that  every AD9640 ic on these boards produces sudden steps.

 


The ADC is initialized on powerup to produce Offset Binary codes. However I also ran the ADC in 2's complement format (by writing through SPI to the control register). In 2's complement mode the output format changes but these small steps still can be seen.

In this above mentioned test the scheme uses a dc coupled connection between the DAC output and AD9640  input.

 

In this test the DAC  produced a saw-tooth wave by running a 14 bit counter inside the FPGA that  samples ADC channel A on ADC_DCOA clock signal (at  25MHz).

The file  dataview.jpg shows the step (shown  in red circle) is actually caused by a simultaneous motion of D7 and D8 bits,  which start to toggle at this location simultaneously. This behavior we can  observe at multiple locations of these sudden steps. And some times the bits  that start to toggle simultaneously are D6 and D7 and some times some other  consecutive bits.

 

The captured data can  be found in “busplot.txt”

The schematic of the  AD9640 can be found in “Schematic.Pdf”


The response is same (that is sudden steps are observed) even if i have AC coupled connecting through AD8352 differential amplifier, as i had performed another test by feeding ADC with a sine wave from external function generator.To add more details here I have observed that these steps are not related with the sampling frequency or frequency of the input signal fed to the ADC. Rather they depends on the voltage level at the ADC input. if i increase sampling frequency i still see as many steps as they were before. and if i increase ADC input signals frequency even then these number of steps remain unchanged. The only thing that changes the number of steps is the peak to peak voltage of the input signal fed to the ADC. if i decrease the input voltage i see less steps.


I request you to please  suggest whats wrong with this ADC chip. Looking forward for your  reply,

 


Thanks and Best  regards,


Asim

 


 

 

 

 

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