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Why are SDRAM accesses that slow ?

Question asked by Mathieu on Jan 6, 2010
Latest reply on Jan 7, 2010 by Andreas

Hi everyone,

 

I am using the BF533 sil.rev 0.6 ; EZ-KIT rev2.2 and, using the emulator i have noticed that SDRAM accesses are very very slow.
Here is my configuration :
- HPUSBICE
- CCLK = 540MHz, SSCLK=108MHz.
- VDSP5 rel 6
- code in L1 memory
- read of 128x16 bit data in non cachable SDRAM bank3 (start@0x01800000).
- use of xml support file included in VDSP
- i have verified in VDSP that SDGCTL=0x8011998D ; SDBCTL=0x0025 and SDRRC=0x01A0.
A code written in assembly only performs a serial of read by using "R0.L = W [ P2 ] ;" with P2 properly initialized.
The thing is that the above instruction (R0.L=...) is executed in 40 CCLK according to the emulator, i.e. 8 SSCLK.
I have verified with a digital scope that the accesses are really that slow.
(SMS stays low for about 10ns and then high for about 60ns.)

 

Hence my questions :
- How is it that the DSP uses as many as 8 SSCLK to make 1x16b transfer ? Shouldn't it be 1 SSCLK ?
- Is that very slow transfer rate normal ? (it corresponds to 14Mw/s)
- What am i doing wrong ?

 

Thanks to those wo can help

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