We are using new hardware that models the Phytec BF-537 implementation. The hardware testing work properly, checknig NVRAM (both parallel and SPI), RAM, ethernet, SDRAM, FPGA access and function, etc and all pass. The change to the XML file for debug loading via the IDDE has been verified and works well. When booting from powerup the load hangs and seems to get stuck in the DMA loading loop forever, or fail with an illegal access trap. I am thinking that the DMA function failed for some reason.
The Boot intializer works fine and is called first prior to the Boot process such that SDram is set up properly.
This software works fine on the ADSP-BF537 and the Phytec BF-537.Both Ver 0.2. After doing a file compare between the 0.2 and 0.3 init code, there seems to be no difference except in the header of the dxe.
I believe we have a fundimental HW issue but am at a loss as to how to isolate it for a fix.
Any ideas would be appreciated.