currently i am working in an 8MByte SDRAM configuration with BF533 Plateform.
I am using single SDRAM for 8MByte.
while writing from blackfin to sdram memory where the higher order and lower order date will store?
Your question can be taken 2 ways.Is your question about high order byte and low order byte? Data is stored in Little Endian order as shown on Page 6-65 of the BF533 Hardware Reference Manual. ABE1# (high byte enable) is used for byte 1 and ABE0# (low byte enable) is used for byte 0.Otherwise you could be asking about the address map. This is a more complicated question. We use the word ‘bank’ to talk about the range of memory space covered by one Blackfin select pin. That minimum organization is 16 megabyte. We also use the word ‘bank’ to refer to internal banks of a SDRAM. The SDRAM memory used can be smaller than 16 Megabyte but the address map gets chopped up into sections as follows.Page 17-46 shows the translation between internal address and SDRAM addresses but it only covers 16 or more megabytes. For a 16-bit 8-megabyte device like the MT48LC4M16A2, this would have 8 column addresses and therefore must be connected like the bottom entry of Table 17-5.
To use all 4 banks internal to the SDRAM, you would not connect the memory row address A12, because there is no such pin on the 8-megabyte device. The result will be gaps in the memory map. In Table 17-5, you see that internal byte address 21 is not connected and will be a ‘don't care’ if it is high or low. The first half of each of the 4 SDRAM banks will be repeated The memory map seen by the processor will be:
First 2megabyte of useable memory
Then 2megabyte of repeated memory (not usable)
Then 2megabyte of useable memory
This memory map gap concept is also discussed in the BF537 hardware manual where an example is given to show the gaps created by using a 2-megabyte device with 2 banks.
I hope that your question was about the address map because it has been fun for me to think about this.
Retrieving data ...