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BF533 : DMA and Cache invalidation

Question asked by Mathieu on Dec 11, 2009


I read somewhere that the data cache was not invalidated after a peripheral to SDRAM DMA transfer.

What about a SDRAM to SDRAM DMA transfer ? I mean, is it the same thing i.e. one have to invalidate data cache at the end of the transfer to make sure that when the processor reads the destination data it actually reads the SDRAM ?

(hope to be clear enough)

Thanks in advance.