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BF534: My initialisation of SDRAM by VDSP fails on real target

Question asked by Colin on Dec 10, 2009
Latest reply on Dec 10, 2009 by Colin

Hi,

  I'm developing a product for the BF534 under Visual DSP 5.0 update 7.

I've started with the BF537 EZKIT.

 

  The code will eventually be too big for internal RAM and so I need to boot

into SDRAM.  I have a small bootload code that loads into L1 space and

correctly initiallises the SDRAM and runs a ram test. This works OK on

both the EZKIT and the real target.

I have some code that, will become the main code, and loads into  both L1

and SDRAM at present.

 

  My problem is the emulator's initialisation of SDRAM.

 

  Under the BF537 EZKIT build, the emulator correctly initialises the SDRAM

on the EZKIT.  I'm using a the "Use XML reset values" of the

Settings/Target_Options menu and also a custom .xml file to set the initial

PC value.

 

  Under the real BF534 I'm trying to set up the same situation.  In this case I

have a custom xml file to define the intial SDRAM controller registers.

After a re-load, the emulator shows the SDC registers with the 'correct' values

and it _doesn't_ generate warnings like:

  "Warning: External memory is disabled for this region of memory."

which it does under other circumstances.

However, the SDRAM is not accessable (at least not writeable), no code

has loaded into it.  The progam hangs in the adi_pwr_program_pll() assembly

routine waiting for the RAM to enter self refresh mode.

 

As far as I can tell the CPU registers are set the same as the

little bootstrap would have set them (PLL registers, EBIU, SYSCFG, SIC)

The 133MHz clock (sclk) is present.

 

It seems that the emulator does something else in setting up the BF on the

EZKIT that I'm not aware of and haven't included in the real target's configuration.

 

Does anyone know where else to look for other configuration that might be missing?

What other registers in the CPU might affect SDRAM access?

 

I should explain that the program I'm trying to run in the target, loads partially into

L1 and into SDRAM and starts executing in L1 with the same initialisation code

that the bootcode uses to set up the target.  It should re-initialse the SDRAM

just as the bootcode does but instead it hangs as described above.

 

 

The RAM is only 8MB and so half of each bank is an image of the low half.

The registers are:

SDGCTL   A011998D

SDGCTL   0001

SDRRC    03A0

SDSTAT   0019

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