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What is the jitter of PCG?

Question asked by Afinko on Dec 8, 2009
Latest reply on Dec 9, 2009 by Mitesh

If I will use the crystal oscillator with freq e.g. 16.384MHz and jitter < 1.1pS as an input to the Precision Clock Generator (PCG) of ADSP-2137x.

What will be the output jitter if I will divide this clock by 4?


I did not found this information in datasheet or hardware reference manual.

They just say, that the jitter will be low, but what is low?


It will introduce a jitter even if I will just "bypass" the input clock with output in SRU (without dividing)?