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BF527: Transferring USB Packets Using DMA.

Question asked by quark on Dec 3, 2009
Latest reply on May 9, 2011 by kiwichris

Hi,

I'm using BF527, Silicon REVISION 0.2

 

When I try to transfer packets from EP1 Rx FIFO to L1 or L3 memory using DMA mode 0, Controller DMA repeat values.

 

See HRM03, page 26-51:

"Peripheral Mode, Endpoint 1, Bulk OUT, Transfer Size Unknown.
Set up an ISR, sensitive to the Rx interrupt, which reads USB_RXCOUNT and then
transfers USB_RXCOUNT bytes (in half words) from the Rx FIFO to the processor core.
This can be performed by configuring the DMA to read the data."

 

Inside Rx ISR:
     ....

     P0.L = lo(USB_RXCOUNT);

     P0.H = hi(USB_RXCOUNT);

     R0 = W[P0] (Z); // R0 = 31 for SCSI CBW.

     P0.L = lo(USB_DMA1COUNTLOW);

     P0.H = hi(USB_DMA1COUNTLOW);

     W[P0] = R0.L;

     R0 = R0 >> 16;

     P0.L = lo(USB_DMA1COUNTHIGH);

     P0.H = hi(USB_DMA1COUNTHIGH);

     W[P0] = R0.L;

     P0.L = lo(USB_DMA1CONTROL);

     P0.H = hi(USB_DMA1CONTROL);

     R0 = (1<<4)|INT_ENA|DMA_ENA;

     W[P0] = R0.L;
     ....

As a result, first two words Controller DMA transfers without errors,
but then it repeat second value three times and next value it repeat again.

Core transfers packets from Rx FIFO without errors when reading register USB_EP1_FIFO.

Is it silicon anomaly or I do something wrong?

Thanks.

 

 

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