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Performance of FIR accelerator

Question asked by MarcS. on Nov 10, 2009
Latest reply on Nov 10, 2009 by DivyaS



I would like to use the SHARC 21469 for professional audio processing. In the last days I dealt with the accelerators.

I want to process the audio samples sample based to minimize the delay. For example I want to use the accelerator for computing a FIR filter with N taps. In the hardware reference I found following formula which describes the performance of the FIR accelerator:


(TCB load + 4 × N + W(N/4 + 2)) × C where:
• N – Number of taps
• W – Window size (--> W = 1 in case of sample based)
• C – Number of channels
• TCB load = 30 peripheral clock cycles
• 4 × N – Number of cycles for loading coefficients and data considering
two cycles for write
• N/4 + 2 – FIR compute cycles considering four pipelined MACs


So in case of sample based processing the overhead for loading coefficients and data (delayline) would be 16 times bigger in comparison to the computation of the FIR filter because for each channel coefficients and data (delayline) have to be reloaded from the internal memory via DMA.

If this is right I would be impossible to use the accelerator for realtime processing in case of 96kHz samplerate.


I would like to know if my conclusion is correct or if there any posibillities to reduce the overhead.


Best regards,