Hi to all
I want to use the PLL to configure the core clock.in the examples of code i saw that the PLL has to be placed in bypass mode and after that its cleared of the bypass mode. Why it should be placed in this mode?
The PLL needs 4096 CLKIN cycles to re-lock to a new VCO frequency incase there is a change in the PLLM value. To make sure that a stable clock is provided to the core till the PLL gets locked, it has to be placed in the bypass mode after changing the PLLM value in the PMCTL register.
For more details on how to re-program the PLL in software,I would also recommend you to refer EE-290.
Hope this helps.
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