I am working on designing a custom baord consisting of Stratix-II FPGA and TigerSHARC ADSP_TS201S.
I am using an auxiliary FPGA Cyclone-II with DSP processor to interface with peripherals.
On referring the ADSP-Ts201S Sytem Design Guidelines Application Note, I found that the power-up
sequence for the DSP processor is such that it only needs to be ensured that the Vdd_dram voltage
(1.6V) is generated last. It says that there isn't any specific obligation to sequencing the generation
of Vdd/Vdd_a (1.2V) and Vdd_io(2.5V). So accordingly, I am following the sequence 1.2V followed by 2.5V
followed by 1.6V. This ensures that 1.6V is generated last.
But when I referred to ADSP-TS201S Silicon ANomaly List - Page 28
58. 03000373 - PLL Failure to Lock at Power-Up:
The PLL may fail to lock correctly to the SCLK input during power-up.
Vdd/Vdd_a must be held low until after Vdd_io and SCLK_Vref are stable and within specification. Additionally, SCLK must be held high
or low until after Vdd/Vdd_a is stable and within specification. The following figure illustrates the workaround (followed by waveforms of sequencing)
According to the waveforms shown, it is required to generate Vdd_io(2.5V) first followed by Vdd/Vdd_a(1.2V).
But such a sequencing hasnt been mentioned in the design guidelines, although PLL power-up is one of the
critical requirements of a DSP-based system.
Can someone please throw light on this workaround? Is it possible to follow the sequencing as I have done presently.
Certain obligations might prevent me from generating 2.5V first unless I make drastic changes in my design.
Thanks and regards,