With reference to my earlier post, wherein I am using ADSP-TS201S with an auxiliary FPGA Cyclone-II, I have an additional question
For SDRAM and FLASH, I am sharing the data bus (D0-D31) of the DSP processor. Now for other peripherals present on my board, the maximum data-width required is 32. And this data-bus is being used to interface via Cyclone-II FPGA i.e. the data path is
ADSP-TS201S -> Cyclone II FPGA -> PERIPHERALS
I am confused as to whether I should use D0-D31 (the same bus used for SDRAM and FLASH) for these peripherals or whether I should use D32-D63 (higher word) data bus. What advantages/disadvantages could I have in either case?
Thanks and Regards,