I am a newbie as far as usage of TigerSHARC processor is concerned.
I am preparing a custom board using ADSP-TS201S and Stratix-II FPGA.
To interface peripherals, I am using an auxiliary FPGA Cyclone-II between ADSP-TS201S and peripherals. Due to certain constraints, I am using 2X16-bit SDRAMs cascaded into 1X32-bit SDRAM. I have cascaded data lines D0-D31 acordingly and using shared address bus and control signals for both.
My question is - Since I am accessing only 32-bit data (word) each time, shal I use only LDQM signal to connect DQML and DQMH signals of both SDRAMs? Will HDQM remain unused in this case, since it is used only for 64-bit data accesses?
Also, the evaluation kit shows using different SDRAM clocks for the two cascaded SDRAMs used. Can I use a single clock source and make connections in a star-shaped format for the same?
Thanks and Regards,