Hi, to all
I saw the ADSP- 21371 EZ KIT Lite manual. I don`t understand the connection of the SDRAM memory. Why the DQM0 - DQM3 are tied trough rezistors?And the BA0 , BA1 to ADDR17/ ADDR18?
Your question about DQM0-DQM3 is valid. The resistors have no value and R24 is not populated on the board. The marking DNP is an American slang notation for Do Not Populate. We get lots of questions about DNP. These SDRAM pins could be connected to ground because all 4 bytes are accessed in parallel. The choice of Bank Address on the highest 2 address lines gives flexibility to the SHARC SDRAM controller as to numbers of RAS and CAS addresses that can be supported.
I desided to use the same SDRAM like int the EZKIT - do i have to connect it by the same way to the ADSP21371?
Forgive me if I confused things when I said:
‘The choice of Bank Address on the highest 2 address lines’
Some of our chips have only 19 address lines. TheADSP-21371 has 24 address lines. The SDRAM controller in the SHARC was designed to use only the first 19 addresses.
So the addressing on your board should be the same as the EZ-Kit. The DQM signals can be connected to ground directly or through a resistor.
You can make your layout life much easier if you also assign the Data Lines (DQ0-DQ31) arbitrarily. It doesn't make any difference to the SDRAM if these lines are scrambled.
DON'T DO THIS WITH THE ADDRESS LINES!
I use a 33 ohm series R in the SDCLK0 line located very near the 21371 (driving end)
As always, use good layout rules and plenty of decoupling. If you serpentine the core supply and the I/O supply plane, you can do it in 4 layers.
Where do i have to determine wich is the address for BA0 & BA1 - is it via configuring SDCTL on the DSP?
Is there any code example for connecting SDRAM to SHARC(21371)?
Savina you can find all the information about how to connect the SDRAM to the ADSP-2137x in:
EE-286: Interfacing SDRAM Memory to ADSP-21368 and ADSP-2137x SHARC Processors
There are also code examples for DMA and Core access, also for code execution from SDRAM for 2137x in:
EE-286: Code example
There are several errors in codes for ADSP-21375 EZ-KIT Lite:
you need to add "seg_epdma0" from "DMA mode.ldf" to the "ADSP-21375-EZKIT.LDF"
and also you need to edit the part of the code in \EE286v04\21375\SDRAM_16_Bit_Interface\Core mode\main.asm:
bit set ustat1 SDCL3|DSDCLK1|SDTRAS6|SDTRP3|SDCAW8|SDPSS|SDTWR2|SDTRCD3|SDRAW12
to the correct one:
bit set ustat1 SDCL3|SDTRAS7|SDTRP3|SDCAW9|SDPSS|SDTWR2|SDTRCD3|SDRAW12|X16DE;
The critical is SDCAW9, because for SDCAW8 only the half of the SDRAM is working (The second half is the mirror of the first one).
All of these settings you can easily find in MT48LC8M16A2 datasheet.
I think that only this one line will differ for 16bit SDRAM for ADSP-21375 and 32bit SDRAM for ADSP-21371, especially the X16DE bit will be erased.
The last error that I found till now in \EE286v04\21375\SDRAM_16_Bit_Interface\DMA mode\main.asm is the line:
bit set ustat2 DIVEN | PLLD2 |PLLM43; /* set a multiplier of 64 and a divider of 3 */
This will run your 266MHz ADSP2137x on the 352,256 MHz.
It was nice to know, that the ADSP-21375 can run at 352,256 MHz, I found these error after several hours of testing this code on 352,256 MHz.
Also the code comments do not correspond with the code itself, but this is normal for almost all of the code examples.
I want to use the SDRAMused in the EZ KIT of ADSP21371. It runs at 166 MHz & 143MHz . How exactly do i have to determine the frequency of the SDRAM. Is it form the ratio of core clock of DSP to SDCLK?
Yes, the SDRAM frequency depends on the core clock. The SDCLK to core clock ratio determines the SDRAM frequency. There are five ratios available in the PMCTL register and you could choose from any of the ratios to get the desired frequency.
SDCKR2 /* CK - SDCLK ratio: 2 */
SDCKR2_5 /* CK - SDCLK ratio: 2.5 */SDCKR3 /* CK - SDCLK ratio: 3.0 */
SDCKR3_5 /* CK - SDCLK ratio: 3.5 */
SDCKR4 /* CK - SDCLK ratio: 4.0 */
Since 21371 runs at the maximum core clock of 266MHz, the maximum SDRAM frequency you can acheive is 133MHz. Also when you change the frequency make sure you have the correct timing values programmed in the SDCTL register based on the SDRAM frequency selected.
thanks for answers. I read about the ratios. Is it problem that the SDRAM runs at 143MHz and the frequency of the SDCLK wich is determined by DSP is 133MHz. Can the SDRAM runs at these 133MHz?
And do i have to configure the core clock by PLL to be 266MHz on 21371?
If the SDRAM you are using is rated for a maximum frequency of 143MHz then it is ok to run the SDRAM at 133MHz. And yes, to acheive the frequency of 133MHz for SDRAM you need to configure the core clock to be 266MHz via PLL programming.
Thanks a lot!!
You can see TIMING SPECIFICATIONS of the processor datasheet.
The frequency of clock in is provided by an oscilator. What is the compatiable voltage of CLKIN? What have to be the oscilator frequency and multiplier & devider to archive 266MHz core clock via the PLL. i want to select one oscilator in farnell.co.uk!!
Or can i determine the Core clock by PLL to be 331.776MHz? And the SDCLK than to be 165.888MHz?
>>The frequency of clock in is provided by an oscilator. What is the compatiable voltage of CLKIN? What have to be the oscilator frequency and multiplier >>& devider to archive 266MHz core clock via the PLL. i want to select one oscilator in farnell.co.uk!!
The VIH_CLKIN and VIL_CLKIN spec is given in the data sheet on page 16.
The range of VIH_CLKIN is 1.74V - VDDEXT+0.5
The range of VIL_CLKIN is -0.5 - 1.10V/
You could use either a crystal or external oscillator . To acheive a 266MHz frequency you can have a ClKIN frequency of 16.625MHz with the multiplier set to 16.
>>Or can i determine the Core clock by PLL to be 331.776MHz? And the SDCLK than to be 165.888MHz?
ADSP21371 is rated for a maximum frequency of 266MHz . You shouldn't operate the DSP higher than the maximum frequency.
I am using an oscilator at 3.3V. And in Farnell.co.uk there is no 16.625MHz but there is 16.384MHz. So i can set the frequency of core clock to be 264MHz with 33MHz oscilator and multiplier of 8 instead! I think that is ok?
You seem to be struggling a bit. This is not unusual for someone doing a first design.
The crystal or oscillator choice is not critical. You are just going to pick a frequency that you can multiply by the PLL to be 266MHz or less.
You can use a crystal, 2 capacitors (22p) and a large resistor for less cost. This is shown in the ADI manual or datasheet.
The choice of the frequency may be important to any peripherals that you are running. For example, are you using a UART at some standard baud?. Are you going to use the DSP clock to drive external data converters?
Is your design targeted for large production (> 1000)? If not, you might be better served by using a board solution from Danville Signal.
We have numerous SHARC boards designed for OEMs including several ADSP-21371 based designs. Contact us if this makes sense.
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