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ADV7393 HSYNC and VSYNC timing diagram for input mode 000

Question asked by bing_wang on Jun 12, 2013
Latest reply on Jun 13, 2013 by GuenterL

Hello,

For the ADV7393, the figure 6 of the datasheet shows the HSYNC and VSYNC timing diagram of SD input, 16-bit 4:4:4 RGB, input Mode 000. Please explain ( or give some reference) the detail of the timing diagram thus I could program FPGA to meet the requirement.

 

Thanks.

 

Bing,

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