AnsweredAssumed Answered

AD9914 Parallel Data Timing

Question asked by BTS on Jun 11, 2013
Latest reply on Sep 11, 2013 by Halausteve

Hi!

I want to use the AD9914 eval board in direct mode via the parallel data port. I need to controle all parameters, means amplitude frequency and phase of the waveform, therefor i decided to use, as described in the manual, two cycles of data, and in the second data i use an i/o update to transfer the data to the core.

i first post the specs of my system, so that you could maybe understand my problem.

 

I use a 3,5GHz clock to drive the AD9914. Therefor my SYNC_CLK should be 3,5GHz/24=145,83MHz.

for the parallel pin controle i use a NI-6535 card with an maximum output samplerate of 10 MHz.

 

The idea was , that i use the maximum samplerate of the Ni-card and use 2 cycles for one output change of the AD9914.

therefor i send 2 samples of information,

the first, with the funktionpins at 0010 for frequency controle and the frequency information (labled in the follwig as F1D1)

the second with the funktion pins at 0101 for amplitude and phase controle, the amplitude and phase data and an i/o update.(F2D2U)

 

it is clear that i lose the half of the sampling rate, means i actually only can use 5MHz, which is still acceptable.

 

the problem is, that when i send an new "doublesample" (one sample freq one ampl and phase) the frequency as well as the amplitude are jumping between several values (means when i send it once it doess not jump, but the information isnt read propperly, so if i send multiple times the freq "jumps with almost each send action)

a little  testing leads to the conclusion, that (maybe) the timing is not correct.

 

since we alternate the data at a frequency of 10 MHz but "look for" new data at a freq of 145MHz.

so what (in my opinion) happens, is that the NI-card doesn't change the new bitpattern fast enough, so that in some cases during the change of the pattern i read information like F1D2 or F2D1, which lead to an unplaned change of the freq or amplitude.

 

to test my theory i used 4 instead of 2 samples, which read as the following:

F1D1

F2D1

F2D2

F2D2U (since also the update bit could be send to early and update the incomplete data during the change)

 

this works fine so far, but as i need 4 samples for one change my all in one samplingrate is now 2,5MHz which is not acceptable anymore.

 

So far my problem. here my suggestions for a reason, or solution of it. It would be nice if you can watch if this makes sense, and if this is realizable with the AD9914.

 

the problem seams to be the different timings of the writing of the NI card and reading of the parallel data port. Since we cant drive the NI-card with more than 10MHz a reduction of the SYNC_CLK would be the only way to change things here. is it possible to change the SYNC_CLK without changing the REF_CLK? Or does it allways run at 1/24 of the REF_CLK

 

the other possible reason would be that the clocks aren't synchronized.

now my questions is: could this be a problem?, also could a synchronization solve the problem?

can i use the slow Ni clk at the sync_in connector at the eval board to synchronize the AD9914 operations with the NI- operations? If yes, do i need any further prgramming (CFR changes for example)

 

the third possible reason could be different lengths of the cables, but that should only be a maximum of a few cm, and i dont think that should be a preblem.

 

thanks for your help

best regards

Daniel

Outcomes