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ADSP-BF609 - MCU RAM initialization

Question asked by Jayapriya on Jun 12, 2013
Latest reply on Jun 12, 2013 by CraigG

Hello ,

This is regarding L2 RAM initialization.

 

When I try to initialize/write into L2 bank memory in core1, I get exception for last three bank access.

It is because those areas are having "CPLB_READONLY_ACCESS" tags.When I modified it to "CACHE_MEM_MODE" it works fine.

Code is as shown below:

 

For Core 1
{0xC8080000, (ENUM_DCPLB_DATA_64KB | CPLB_DNOCACHE)},
   {0xC8090000, (ENUM_DCPLB_DATA_64KB | CPLB_READONLY_ACCESS)},
   {0xC80A0000, (ENUM_DCPLB_DATA_16KB | CPLB_READONLY_ACCESS)},
   {0xC80A4000, (ENUM_DCPLB_DATA_16KB | CPLB_READONLY_ACCESS)},
   {0xC80A8000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80AC000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80B0000, (ENUM_DCPLB_DATA_64KB | CACHE_MEM_MODE)},

 

After change
   {0xC8080000, (ENUM_DCPLB_DATA_64KB | CPLB_DNOCACHE)},
   {0xC8090000, (ENUM_DCPLB_DATA_64KB | CACHE_MEM_MODE)},
   {0xC80A0000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80A4000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80A8000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80AC000, (ENUM_DCPLB_DATA_16KB | CACHE_MEM_MODE)},
   {0xC80B0000, (ENUM_DCPLB_DATA_64KB | CACHE_MEM_MODE)},

 

Is it fine to modify app_cplbtab.c ??

 

Thanks,

Jayapriya

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