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Xilinx zynq design for zedboard using obsolete processor system model

Question asked by milosoftware on Jun 11, 2013
Latest reply on Jun 12, 2013 by milosoftware

The design for the zedboard as posted here:


is still using the "3.00.a" version for the "processor_system_7" component. This results in a lot of wasted FPGA resources in any image based on this design, as that version doesn't properly forward the clock information. The design for the zc702 does not have this problem, it is properly using the 4.02.a version.


I tried simply upgrading the processor to 4.02.a (for the 14.4 Xilinx ISE tools) or 4.03.a (for the 14.5 version of ISE), but this resulted in failure to meet timing requirements on the 200MHz clock parts.


Is any work being done on these designs? In particular:

- Are you aware of this fault in the zedboard design? And will it be fixed?

- Will the DMA engines be updated to newer versions?

- Will there be versions for ISE 14.5 and the future Vivado versions?