We have an A/D "end of conversion" output tied to IRQ0/FLAG0 pin on the processor. We are using the shadow register technique to allow for the fastest possible interrupt response with lowest latency. We are also using interrupts for UART Receive on Programmable Interrupt 13. Since we're using the shadow register technique for our end-of-conversion interrupt, we can not have nested interrupts during that time (and would not want to anyway).
So far we've exercised the system quite a bit and never ran into a problem, so it seems that IRQ0/FLAG0 is never being interrupted by the UART Receive interrupt.
I guess the crux of the question is about interrupt priorities. Does IRQ0/FLAG0 simply naturally have a higher priority than others?