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Detecting a Rising Edge - SHARC Assembly

Question asked by cconrad on Jun 7, 2013
Latest reply on Jun 17, 2013 by Harshit.Gaharwar

Greetings,

 

 

I'm trying to block until the rising edge of a Flag pin (Low to High), which is driven by a PCG timer square wave.  This code works fine:

 

flg_high:  BIT TST FLAGS FLG10;

           IF TF JUMP flg_high; 

flg_low:   BIT TST FLAGS FLG10; 

           IF NOT TF JUMP flg_low;   

 

except there is cycle jitter associated with it.  Since it's a two cycle test, depending on where the CPU is in relation to the edge

you will get a 1 or 2 core cycle delay coming off the edge.

 

I'm trying to tighten this up this loop by using the zero overhead looping:

 

DO flg_high UNTIL TF;                      

flg_high:   BIT TST FLAGS FLG10;   

DO flg_low  UNTIL NOT TF;                             

flg_low:          BIT TST FLAGS FLG10;

 

Now my jitter does go away, however this loop seems to be detecting High to Low to High, instead of just

Low to High.  That is, depending on how late I start this in the cycle it will count every cycle, or every other cycle. 

I'm sure there is something I'm not understanding about the sequencer, test, and cache.  Can someone enlighten me?  Thanks,

 

PMT

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