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Can not display image in ADV7511 reference design on ZC706

Question asked by lupin on Jun 5, 2013
Latest reply on Jun 30, 2013 by lupin

I use the xilinx board ZC706(Rx) to run your reference disign about ADV7511 which provide from your website:

"ADV7511 XILINX EVALUATION BOARDS REFERENCE DESIGN"  version (26 Apr 2013 10:35)

It suppose can display an demo image and play a sound.

I download no-OS Software and HDL reference design as below website,

"ADV7511 ZC706 Reference Design: https://github.com/analogdevicesinc/no-OS/tree/master/ADV7511_ZC706" and

"ADV7511 ZC Library: https://github.com/analogdevicesinc/no-OS/tree/master/ADV7511_Library/ZC"

"ZC706 HDL Reference Design: cf_adv7511_zc706_edk_14_4_2013_02_05.tar.gz"

 

 

I build "sw.elf" on xilinx SDK to run on board ZC706

After executing my monitor show "OUT OF RANGE".

I switch resolution to "1280X720" my monitor show "NO SIGNAL"

 

 

Do you have any suggestion for this problem?

 

Here are the messages shows on the console after running:

 

 

********************************************************************

  ADI HDMI Trasmitter Application Ver R1.1.1

  HDMI-TX:  ADV7511 Rev 0x14

  Created:  Jun  6 2013 At 10:06:46

********************************************************************

 

 

To change the video resolution press:

  '0' - 640x480;  '1' - 800x600;  '2' - 1024x768; '3' - 1280x720

  '4' - 1360x768; '5' - 1600x900; '6' - 1920x1080.

Mute audio and video.

APP: Driver Enabled

HPD changed to HI

MSEN changed to HI

A new EDID segment was read.

------------------------- EDID BLOCK 0 -------------------------

Edid Version 1.3

Mon Timing:

    Pixel clock = 148.50 MHz

    H Active    = 1920

    V Active    = 1080

    Progressive

    No stereo

    Separate sync = 3

    +ve VSync

    +ve HSync

Mon Freq:

    Min V Freq = 50 Hz

    Max V Freq = 76 Hz

    Min H Freq = 30 KHz

    Max H Freq = 83 KHz

Mon Name:   VE246

 

 

Mon Serial: A9LMQS016906

 

 

Edid extensions blocks: 1

 

 

========================= EDID BLOCK 1 =========================

CEA extension block revision 3

Underscan=Yes  Audio=Yes  YCbCr4:4:4=Yes  YCbCr4:2:2=Yes

Data block collection information:

    Video data block

       * VIC=16

         VIC=5

         VIC=4

         VIC=3

         VIC=2

         VIC=1

         VIC=17

         VIC=18

         VIC=19

         VIC=20

         VIC=31

    Audio data block

       Format Code          = 1 (Linear PCM)

        Max. No. of Channels= 2

        Sampling Freq. (KHz)= 32  44.1  48

        Length (bits)       = 16  20  24

    Speaker allocation data block

       0x01

       0x00

       0x00

    VSDB data block

SPA location is at 0x9C, SPA = 1.0.0.0

Mon Timing:

    Pixel clock = 138.50 MHz

    H Active    = 1920

    V Active    = 1080

    Progressive

    No stereo

    Separate sync = 3

    -ve Vsync

    +ve HSync

Mon Timing:

    Pixel clock = 85.50 MHz

    H Active    = 1366

    V Active    = 768

    Progressive

    No stereo

    Separate sync = 3

    +ve VSync

    +ve HSync

Mon Timing:

    Pixel clock = 74.25 MHz

    H Active    = 1280

    V Active    = 720

    Progressive

    No stereo

    Separate sync = 3

    +ve VSync

    +ve HSync

Mon Timing:

    Pixel clock = 27.0 MHz

    H Active    = 720

    V Active    = 480

    Progressive

    No stereo

    Separate sync = 3

    -ve Vsync

    -ve HSync

Mon Timing:

    Pixel clock = 74.25 MHz

    H Active    = 1920

    V Active    = 540

    Interlaced

    No stereo

    Separate sync = 3

    +ve VSync

    +ve HSync

########################### EDID END ###########################

 

 

APP: Changed system mode to Transmitter

Un-mute audio and video.

Resolution was changed to 1280x720

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