Two questions about SHARC 21488:
1. VDD_INT range, from the data sheet, VDD_INT's range is 1.05V ~ 1.15V, but in that range, DSP works abnormal which causes JTAG can't work as expected, for example ICE test is ok, and emulator session can connect with target, but if build project and load program to target, then VDSP will show message " Failed to set automatic breakpoint at "main". We use 12.288 exteranl crystal and CLK_CFG1/0 = 0b10 BOOT_CFG2/0 = 0b000 after power up.
a) If change CLK_CFG1/0 to 0b00, then JTAG can work - load program and stop at main entry. in this case if config PLL as 32x in program, then DSP crash right now if BYPASS bit is clear in PMCTL.
b) if increase VDD_INT to 1.5V, then JTAG also can work - load program and stop at main entry, in this case if config PLL as 32x in program, and SP can work, I can verify SDRAM write and read ok. and LED controled by FLG0 in DSP timer blinks as expected.
My question is how to check this issue? how to make dsp work with standard VDD_INT?
2. Multiprocessor example, I'm using VDSP++ 5.0 and update 10.1, and now I have 3 sharc 21488 in sequential order. Anybody can supply a multiprocessor example project for reference? The project in EE-148 can't be opened in VDSP++ 5.0.