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PLL not work with cclk>125MHz on ADSP-21489

Question asked by SergeyB on Jun 4, 2013
Latest reply on Jun 7, 2013 by MaheshN

Hello! I wrote the program for the board with ADSP-21489 and it worked fine with the ADC, UART, IIR accelerator at 400MHz. Recently, I tried to program the same five boards, but I have a problem with PLL with all of them!. They are don't get the frequencies above 125 MHz. I used the debugger USB-ICE. And on the debug board EZ-KIT-21489 this project runs fine on 400MHz!


Schematic of my board is very similar with EZ-board. CLKIN Generator = 25MHz


I decided to change my own initialization code to the one in the example of "EE-290: Code Example (Rev 5, 03/2012) (zip, 181 kB)"

I used this function:

initPLL_2148x (16,1,1, false);

And it works properly with frequencies less than 125MHz


initPLL_2148x (5,0,1, false);

works (CCLK = 125MHz, VCO = 250MHz)


initPLL_2148x (6,0,1, false);

dont work! (CCLK = 150MHz, VCO = 300MHz)


With JTAG debugging, run the program it hangs up, or place the pointer disappears when the program is stopped.


I also control CCLK by checking UART baudrate and ADC data.

CLK_CFG pins are initialized, connected to the earth, so CRAT = 00.

Power voltages and RESET checked by osciloscope, all is good in all states.


Help me please! Maybe thic IC's have anomaly???