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Large gate count reduction possible on Zynq FMCOMMS1 if synchronous bus interconnects are used

Question asked by jay_d on Jun 3, 2013
Latest reply on Jun 5, 2013 by jay_d

Large gate count reduction possible on Zynq FMCOMMS1 design with synchronous bus interconnects,

 

  One of the problems I have seen with the XC702 FMCOMMS1 FPGA design is its large usage of gates to build the AXI bus interconnect cores.  As it turns out Xilinx XPS/EDK cannot figure out the logic interconnection sections are using synced clocks if the ARM PLL is used to generate the clocks. Currently the XPS/EDK tool makes these interconnect interfaces asynchronous where huge amount of logic is used if the ARM PLL clock system is used instead of a embedded logic area PLL clock system. Using  the ARM PLL causes about 91%  of the gates to be used in default FMCOMMS1 base design on XC702 or ZED. Whereas changing to use a embedded logic PLL clock, like in used in FMCOMMS1 KC705, the number logic gates used in the 702 Zynq default FMCOMMS1 drops down to 63%.  It seems that the only way XPS can build a system with synchronous interconnects is to use a embedded logic area PLL or MMCM clock system.

  The amount of area used for the AXI interconnects goes to almost nothing if it they are built as a synchronous ones. A entry in the processor mhs instance can then be used to force any given interconnect path to be asynchronous if needed for some reason.

 

  I have noticed the XPS/EDK builds generated warning messages about this...

   WARNING:EDK:3712 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0 - Frequency of the interconnect's clock port could not be determined. All IPs in the design will be considered to be asynchronous with respect to the interconnect. This will lead to more resource usage. You can avoid this by specifying the clock frequency on the port that the interconnect's clock is connected to.

.. ..

WARNING:EDK:3712 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_4 - Frequency of the interconnect's clock port could not be determined. All IPs in the design will be considered to be asynchronous with respect to the interconnect. This will lead to more resource usage. You can avoid this by specifying the clock frequency on the port that the interconnect's clock is connected to.

 

  I Know  the number of gates being used for the interconnect in the Zynq is huge for FMCOMMS1 design up in PlanAhead with my highly altered hdl design at this point. I been try to figure this out for awhile. Going back and studying the Xilinx base reference design system.mhs for the Zynq I noticed they used a embedded logic area PLL clocking and not the ARM PLL clocking.

  So, following the Xilinx base reference design and  FMCOMMS1 KC705 I changed my design system.mhs for XC702 to use the 200MHz clock input, a embedded logic area PLL, and extra PLL lock delay Reset controller. Now a whole lot of gates disappear and it builds really fast. 

 

ZC702/FMCOMMS1 gate usage XPS/EDK 14.5 build as asynced interconnect interface, ARM PLL.

no HDMI spdif , no chipscope,  default FMCOMMS1 pcores without alterations to use DSP48, and  

no floor plan built in XPS/EDK

  --Number of Slice LUTS                  25302 out of 53200  47%

  --Number of Slice LUT-Flip Flop pairs   33246 out of 53200  62%

 

ZC702/FMCOMMS1 gate usage XPS/EDK 14.5 build as synced interconnect interface, embedded logic PLL.

no HDMI spdif , no chipscope,  default FMCOMMS1 pcores without alterations to use DSP48, and  

no floor plan built in XPS/EDK

  --Number of Slice LUTS                  16909 out of 53200  31%

  --Number of Slice LUT-Flip Flop pairs   21439 out of 53200  40%

 

ZC702/FMCOMMS1 gate usage XPS/EDK 14.5 build as synced interconnect interface, embedded logic PLL.

no HDMI spdif , no chipscope,  FMCOMMS1 pcores changed to use DSP48 for mul.v in HDMI 16 video and muladd.v in ADC. No floor plan built in XPS/EDK

--Number of Slice LUTS                  15026 out of 53200  28%

--Number of Slice LUT-Flip Flop pairs   20249 out of 53200  38%

 

Note that removing the HDMI spdif and DMA for it opens up the Zynq HP1 DMA channel port and space. This requires removal of HDMI spdif, its DMA, and related audio instances in the Linux devicetree also.

 

  Can send to ADI team example ZC702 system.mhs and ucf  that has HDMI spdif removed and uses logic area PLL. Also I have working DSP48 multiplier and multiplier/adder Verilog base macro replacements for ADC and HDMI16 pcores that might be of interest. 

 

  As to why the XPS/EDK tool does not understand how to build synced interconnect interfaces when using the ARM PLL for system clocks is something Xilinx might be able to answer. 

 

Thanks,

James

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