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AD9739 data port timing

Question asked by briankomo on Jun 3, 2013
Latest reply on Jun 3, 2013 by danf

I have a customer with the following question:

 

"I see according to the datasheet that the Minimum LVDS valid window is 344 ps and the recommended guard band is 100 ps, so how would I go about figuring out the setup and hold time that would be need for the Xilinx Vivado tool?

 

In Vivado they are looking for min value (hold) and max value (setup) for both rising edge and falling edge.

 

The DCI frequency I am outputting from the FPGA is 325 MHz."

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