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AD9963-EBZ and Xilinx ML605

Question asked by invisible1NK on May 31, 2013
Latest reply on Jun 19, 2013 by invisible1NK

Hello! I am a new member of this forum and I hope someone can help me solving a problem.

 

I am working with "AD9963" Evaluation Board and using the "AD FMC adapter" to connect the board with the Xilinx FPGA virtex 6 ML605. I want to convert the digital signals of my FPGA system into the analog domain using the two channel available DACs. I will observe the DAC output signals with an oscilloscope (BW= 40MHZ at 500MS/s).

 

The data that i am sending through the FMC connector is: TXD (12-bit data vector), TXIQ (control signal for channel selection) and TXCLK (clock with twice the frequency at which the data is generated).

The UCF file in my FPGA system was built as follows: For example, TXCLK will match the FPGA output pin K26, which is related to the G6 pin of the FMC-LPC connector (in virtex 6). In the "AD FMC adapter", the G6 pin corresponds to A2 pin of J17 side (TXCLKI_CMOS). The same strategy was used for the remaining signals. The selected IOStandard was "LVCMOS".

 

I am also using a "SMA_USER_GPIO_P" connector in ml605 to output a clock to the "main clock input" of the board (DACCLK). This clock has got one half of the TXCLK speed. (For example, TXCLK is a 10MHz signal and DACCLK is 5MHZ signal. They are synchronous.)

 

Finally, I am configuring the AD9963 registers via SPI interface using the "SPI application" provided by Analog Devices CD. I have tried "half-duplex" and "full-duplex" modes, with no success. I am attaching a file with the list of register parameters that I introduced for "full duplex mode".

 

I cannot visualize any signal in the two SMA output of the DACs. Do you have any suggestions for this situation?

Thank you for the attention,

 

Greetings

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