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AD-FMCOMMS1-EBZ + AD9548 problem (ZC702)

Question asked by calex on May 30, 2013
Latest reply on Sep 5, 2013 by ACozma



i need to use a reference clock coming from the FPGA to drive the AD9548.

When i read the schematics, i find the differential signal 9548_ref signal coming

from the FMC connector used as REFA. So i supposed that the clock generator uses it,

but in fact, it runs in freerun mode and you always get a 122.88 MHz signal on J9 and J10

even if you remove the 9548_ref signal. The digital PLL core is not used and the effective ref clock

is the 19.2 MHz TCXO on the board and not REFA.


Do you have a C code (AD9548.c, AD9548.h) to configure the AD9548

in order to use REFA ?