I am looking for a solution to encode 16 video channels in MJPEG
Do you provide this type of solution ?
Multiple instances of the JPEG encoder can be used in an application, but ADI does not provide a multi-channel example for a motion-JPEG encoder.
MIPS/memory requirements will depend on the system's required video resolution, the video data format, video frame rate, and desired quality of encoded video. To illustrate processor requirements, let's assume that black and white video (8 bit monochrome) at a resolution of 352 x 288 (CIF) needs to be encoded for each of the 16 channels. Let's also assume that the JPEG images are only encoded in sequential mode (which reduces memory requirements), and that a low-ish quality factor is used, say 40 (which reduces MIPS requirements).
In terms of memory, the JPEG encoder spec sheet KT-571 says that code size is ~12 KiB, data tables is ~4 KiB, and ~2KiB per instance from dynamic memory. For 16 instances, this adds up to a total of:
12 + 4 + 16 * 2 = 48 KiB
In addition, input/output buffers are required - each 352x288 monochrome video frame uses ~101 KiB, while for the compressed bit stream, if we assume a compression ratio of 10, then 10 KiB is needed for each frame per channel. Buffering just one input/output frame for each channel uses a total of 1.8 MiB
In terms of MIPS, the spec sheet quotes performance figures for encoding images in YUV420 format where each pixel is represented by 12 bits of information. For monochrome format, we only have 8 bits of information for each video pixel, so an estimate of MIPS for encoding monochrome frames is 67% of that for YUV420 frames. At a quality factor of 40, the peak cycles per pixel (YUV420) is 65 when all code/data is in cached external memory. So peak number of cycles per frame per channel is 65 * 352 * 288 * 67/100 = 4.4 Mcycles.
If we assume a frame rate of 15 fps, then the total peak MIPS usage is:
16 * 4.4 * 15 = 1060 MIPS
The estimated MIPS and memory usage indicate that a BF561 is suitable where half the channels could be handled by one core, and the remaining channels handled by the other core.
This thread has been moved from the General DSP Discussions category. Please continue the discussion here. Thank you.
What resolution and frame rate do you need? I assume that all channels need to run simultaneously. What chipset are you designing for?
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